The present invention relates, in general, to the field of delay locked loops (“DLLs”). More particularly, the present invention relates to an analog delay locked loop in which the voltage-controlled delay through the analog delay line is initialized at or near the minimum possible delay.
Delay locked loops (DLLs) are known in the prior art. A delay locked loop is a type of control loop that adjusts a variable delay line to maintain minimum phase error between an output sync clock signal and an input reference clock signal. The object of a delay locked loop is to add an integer number of clock periods of delay to an undelayed clock signal in order to create a delayed replica clock signal that is in phase with the undelayed clock signal. The delay control is achieved either through voltage control of an analog delay line or through digital control of a digital delay line.
An example of a prior art analog delay locked loop can be found in U.S. Pat. No. 6,346,839 B1, to Mnich entitled “Low Power Consumption Integrated Circuit Delay Locked Loop and Method for Controlling The Same”, which is hereby incorporated by reference. In particular, FIG. 1 of the '839 patent, which is reproduced as FIG. 1A in the present application, is a simplified block diagram of a delay locked loop 10 including a voltage controlled delay line 12, a fixed delay line 14, a delay voltage control 16A, phase detector 18A, fast/slow latch 22A, and integrating capacitors C0 and C1. The phase detector 18A generates “Go Fast” and “Go Slow” control signals that are received by the fast/slow latch 22A. In turn, fast/slow latch 22A generates “Latched Fast” and “Latched Slow” control signals that are received by the delay voltage control 16A.
In the prior art delay locked loop 10 shown in FIG. 1A, there is a potential for the phase detector 18A to indicate that the delay through the delay line 12, 14 should be reduced via the voltage controlled delay line 12 when it is not possible to achieve a lock condition by reducing the delay, because the minimum achievable delay exceeds the delay needed to achieve a lock condition. In addition, the delay at which the DLL 10 locks may not be the minimum possible delay for the range of delays available, because of the requirement to set a relatively long initial delay in order to address the non-locking condition described above. Setting a long initial delay causes jitter to be higher than it would be if the lock point were set at a shorter delay point.
In the prior art DLL 10 shown in FIG. 1A, the probability of the non-locking condition described above occurring is minimized by adding flip-flop delay elements in the CLOCK path of phase detector that are not in the SYNC path as shown in FIG. 5 of the '839 patent. This causes the so-called “Go Slow” signal, “SLW,” to occur before the “Go Fast” signal, “FST,” on start-up or after DLL 10 is reset. The phase detector 18A is in turn reset when the first FST signal occurs. The so-called “fast/slow latch” circuit 22A assures that only a “latched slow” signal, “SLWL” occurs. In most cases, this assures that the SLWL signal occurs in each subsequent cycle until DLL 10 reaches a locked condition. However, if the initial delay through the total delay path 12, 14 of DLL 10 is such that the rising edge of the CLOCK signal input to phase detector 18A is close enough before the rising edge of the SYNC CLOCK signal, phase detector 18B cannot reset fast enough after the first occurrence of the FST signal and the next rising edge of the SYNC CLOCK signal will be ignored. When this happens, only the “Latched Fast” signal “FSTL” signal continues to occur in each subsequent cycle until DLL 10 reaches a lock condition—if the delay can be reduced enough to lock. If the required delay to lock is shorter than the minimum achievable delay through the delay line 12, 14, DLL 10 will not be able to lock.
In order to further minimize the probability of the “non-locking” condition described above, the initial delay through the delay line 12, 14 is set so that for the frequencies of interest, DLL 10 is able to achieve a locked condition even if a FSTL signal occurs with the first and subsequent FST signals. However, it is difficult to establish such an initial delay over all process, voltage, and temperature conditions. Furthermore, in order to allow for a decision that the delay through the delay line 12, 14 should be reduced, the initial delay of the delay line is ideally set to a relatively long delay in order to allow locking to be achieved at a shorter delay. If DLL 10 is not initialized to or near its minimum delay, but rather at the preferred “long” initial delay, there is a chance of not having the shortest or optimum delay solution for a given clock frequency. Locking at long delays makes DLL 10 more susceptible to jitter due to power and ground noise.
Digital delay locked loops are known in the prior art that have the initial delay set to a minimum value and incrementally increase the delay. However, digital delay lines have less phase resolution than voltage controlled (analog) delay lines. Furthermore, in digital delay locked loops there exits a possibility of missing a transition to a mode in which the delay must be allowed to be reduced as well as increased in order to maintain a locked condition. This missed transition is more likely in a digital delay loop because of the incremental size of the digital adjustments and the nature of the circuit used to detect the transition. In order not to miss this transition, a so-called “time window” is created in the phase detection circuit that is longer than the adjustment increment. Setting a time window over all voltage, temperature, and process variations is difficult to achieve. Clock jitter can also cause the delayed signal to move outside the time window and lock will be lost. An adjustment of one delay increment (for example, using multiple gate delays) made in every clock cycle as the delayed clock moves in and out of the time window when the DLL is locked can result in substantial jitter.
Other known digital delay lines in the prior art have attempted to address the problem of missing the transition to the case where the delay must be decreased by making the allowable time window much wider. To achieve this, the loop of the DLL can be opened prior to the time the delayed signal's rising edge falls into the time window and the loop is closed after the rising edge falls inside the time window. The phase detector of the DLL is only used to determine when the delayed signal has fallen inside the time window initially and only begins to control the delay of the delay line after that point. A significant amount of additional circuitry is required to determine when the delayed signal is inside the time window and to control the transition between the dual mechanisms used for controlling the delay of the delay line.
What is desired, therefore, is an analog delay locked loop circuit that avoids the problems inherent to digital delay locked loop circuits, as well as the jitter and non-locking condition problems associated with certain prior analog delay locked loop circuits.